sicp-ex-3.29

genovia

 ;;or-gate implementation  : https://en.wikipedia.org/wiki/OR_gate 
  
 (define (or-gate a1 a2 output) 
   (let ((c (make-wire)) 
         (d (make-wire)) (e (make-wire)) 
         (f (make-wire) (g (make-wire)))) 
     (and-gate a1 a1 d) 
     (and-gate a2 a2 e) 
     (inverter d f) 
     (inverter e g) 
     (and-gate f g c) 
     (inverter c output) 
     'ok))

meteorgan

  
  
 ;; a 
 ;; (A or B) is equivalent to (not ((not A) and (not B))) 
 (define (or-gate a1 a2 output) 
   (let ((c1 (make-wire)) 
         (c2 (make-wire)) 
         (c3 (make-wire))) 
     (inverter a1 c1) 
     (inverter a2 c2) 
     (and-gate c1 c2 c3) 
     (inverter c3 output))) 
  
  
 ;; b 
 the delay is the sum of and-gate-delay plus twice inverter-delay.

Sphinxsky

the delay is the sum of and-gate-delay plus triple inverter-delay.

dzy

twice. because only one of a1,a2 changes so that inverter only act once.

squarebat

Even if both inputs were to change simultaneously, the delay would still be twice inverter + and delay, since both inverters for the input wires work at the same time.